Bipolar transistors have been used in semiconductor devices for quite some time and are becoming more and more common with an increasing popularity of BiCMOS (bipolar-complementary metal oxide semiconductor) devices. In BiCMOS devices, bipolar transistors and CMOS transistors are fabricated together in a single semiconductor device. To simplify BiCMOS device fabrication, it is advantageous to integrate as many CMOS processing steps with bipolar processing steps as possible.
A bipolar transistor structure which can be easily integrated into a traditional CMOS process is a single polysilicon bipolar transistor with self-aligned base and emitter regions. This bipolar transistor, which will hereinafter be described as an NPN bipolar transistor, includes a polysilicon emitter electrode which is formed on a P.sup.- active base region of a substrate. The polysilicon is doped with N-type impurities such that an N.sup.+ emitter region is formed in the active base region, aligned to the emitter electrode, as a result of out-diffusion. A link implant is performed to form P.sup.- link regions in the substrate which are aligned to edges of the emitter electrode and are contiguous with the active base region. Sidewall spacers are then formed along edges of the emitter electrode, and a P.sup.+ implant is used to form extrinsic base regions which are aligned to the sidewall spacers and are contiguous with the link regions.
The above bipolar transistor is easily incorporated into a CMOS process; however, there are a few disadvantages in using this bipolar transistor. From a fabrication point of view, the single polysilicon bipolar transistor requires a difficult etch process, namely that of etching the polysilicon emitter electrode selective to an underlying silicon substrate. Etching polysilicon selective to silicon is nearly impossible to do with existing technology without trenching portions of the silicon substrate. With respect to electrical performance and reliability, the single polysilicon bipolar transistor has unfavorably low emitter-base breakdown voltages because the N.sup.+ emitter region and P.sup.- link region often laterally diffuse into one another. Another disadvantage is that under reverse-bias conditions, the single polysilicon bipolar transistor is susceptible to HCI (hot carrier injection) damage due to high electric fields at the emitter-base junction, leading to a reduction in gain (also known as .beta. degradation).
A further limitation to the single polysilicon bipolar transistor is a restricted ability to scale the transistor. Following the overall trend in the semiconductor industry, dimensions of bipolar transistors will continue to be reduced. Accordingly, doping levels of the active base, extrinsic base, emitter, and link regions will increase in order to maintain existing levels of performance. However, as doping levels increase, the aforementioned problems will worsen. More specifically, emitter-base breakdown voltages will become lower, while damage due to HCI will increase. Reducing the size of the transistors will cause sidewall spacers used to align the extrinsic base region to be made narrower. The extrinsic base region, as a result, will be brought in closer to the emitter region, thereby further lowering emitter-base breakdown voltages and further increasing electric fields at the emitter-base junction.